Some embodiments relate to methods of manufacturing a semiconductor device. More particularly, some embodiments relate to methods of manufacturing a semiconductor device including a metal oxide semiconductor (MOS) transistor having a reduced overlapping capacitance.
Generally, as semiconductor devices become more highly integrated, short channel effects in MOS transistors have become more problematic. In order to reduce the prevalence of short channel effects, source/drain regions of MOS transistors have been formed to have a lightly doped drain (LDD) structure.
FIG. 1 illustrates an LDD structure formed by using an offset dual spacer (ODS).
The LDD structure illustrated in FIG. 1 may include two offset spacers 25 and 40 formed on side walls of a gate electrode 15 formed on a substrate 10. At the bottom portion of the gate electrode 15, a gate oxide layer 12 may be formed, and at a side wall of the gate electrode 15, a side wall oxide spacer 20 may be formed. By using the two offset spacers 25 and 40, a lightly doped impurity region 30 and a highly doped impurity region 45 may be formed.
FIG. 2 illustrates an LDD structure formed by using an offset single spacer (OSS).
The LDD structure illustrated in FIG. 2 may include one offset spacer 25 formed on a side wall of a gate electrode 15.
Referring to FIGS. 1 and 2, the ODS and OSS LDD structures may have little difference in terms of a shape of the spacers and a shape of impurity regions. However, the LDD structures show a very large difference in electric characteristics. The differences in the electric characteristics of MOS devices including ODS and OSS LDD structures are shown in FIGS. 3 to 8.
FIGS. 3 to 5 illustrate graphs for comparing a current, a driving voltage and a gate overlapping capacitance value of each NMOS transistor having an LDD structure formed by using an ODS or an OSS.
Referring to FIG. 3, the NMOS transistor formed by using the OSS shows a slight decrease but no improvement of a driving current when compared to the NMOS transistor formed by using the ODS.
Referring to FIG. 4, the NMOS transistor formed by using the OSS shows an improvement in an average driving voltage by about 5 mV when compared to the NMOS transistor formed by using the ODS.
Referring to FIG. 5, the NMOS transistor formed by using the OSS shows a decrease of a gate overlapping capacitance value by about 3.0% when compared to the NMOS transistor formed by using the ODS.
FIGS. 6 to 8 illustrate graphs for comparing a current, a driving voltage and a gate overlapping capacitance value of each PMOS transistor having an LDD structure formed by using an ODS or an OSS.
Referring to FIG. 6, the PMOS transistor formed by using the OSS shows an improvement in a driving current by about 7.44% when compared to the PMOS transistor formed by using the ODS.
Referring to FIG. 7, the PMOS transistor formed by using the OSS shows an improvement in an average driving voltage by about 67 mV when compared to the PMOS transistor formed by using the ODS.
Referring to FIG. 8, the PMOS transistor formed by using the OSS shows a decrease of a gate overlapping capacitance value by about 3.65% when compared to the PMOS transistor formed by using the ODS.
As described above, the performance of a transistor having an LDD structure including an OSS structure may be improved compared to transistors having an ODS structure. However, for manufacturing a dynamic random access memory (DRAM), commonly applicable processes for manufacturing a MOS transistor having an LDD structure using an OSS structure may be very complicated.
In particular, when an offset spacer layer is formed on a side wall of a gate electrode and on a substrate in a peripheral region, the offset spacer layer may also be formed on a bit line and on the substrate in a cell region. Since the formation of the offset spacer may not be necessary on the side wall of the bit line in the cell region, the cell region may be covered using a photoresist layer pattern by performing a photolithography process before etching the offset spacer layer anisotropically to form the offset spacer in the peripheral region.
Then, an anisotropic etching process with respect to the offset spacer layer in the peripheral region may be performed to form the spacer on the side wall of the gate electrode. Thereafter, a lightly doped impurity region may be formed and an additional oxide layer spacer may be formed. Then, a highly doped impurity region may be formed.
As described above, an additional photolithography process may be required for selectively covering the cell region before forming the lightly doped impurity region in the peripheral region. In addition, the area of a bottom portion of a contact plug formed between the bit lines may be decreased due to the offset spacer layer that remains on the side wall of the bit line in the cell region.